Power dissipation in CMOS digital circuits
The growing development of CMOS logic VLSI circuits has decreased the circuit size, increased the switching speed , there is one problem associated with this technology that is known as the power dissipation . There are many researchers who are trying to decrease the power consumption of CMOS based digital circuits. The main cause of power dissipation in CMOS based VLSI circuits are divided on the basis of its working or behavior.
There are mainly two cases of Power dissipation 1) Dynamic power dissipation 2) Static power dissipation. This dynamic power dissipation can be further divided in three parts known as switching power dissipation, short circuit power dissipation and glitching power dissipation. These can be reduced by changing the parameters of the following models:
P switching = α Foperating.Vdd2 CL [for full output swing]
Where Foperating is operating frequency, Vdd = supply voltage, CL= Net load capacitance, α= switching activity factor of gate.
P switching = α Foperating Vdd. Vswing CL [for low voltage swing]
Short circuit power
Pshort circuit = (μCox/12) (W/L)(Vdd-2Vth)3τ Foperating
Where τ = rise/ fall time of the input signal
The static power dissipation occurs because of two reasons: DC current and Transistor leakage current.