Wednesday, July 2, 2014

Design a Single Precision Floating Point Unit

A single precision floating point unit in verilog is introduced. The novelty of a single precision floating point unit is to provide five arithmetic operations: addition, subtraction, multiplication, division, and square root. In top-down design approach, four arithmetic modules: addition/subtraction, multiplication, division, and square root are combined to form a single precision floating point unit. Each module is independent from each other. The modules are realized and validated using verilog simulation in the Modelsim SE 6.5 and synthesis using Xlinx ISE Design Suite 13.3.

The single precision floating point unit implemented, is a 32-bits processing unit which allows arithmetic operations on a floating point numbers. The floating point unit complies fully with IEEE 754 standard.

Author - Akash Kumar 
(Research Associate at SiliconMentor)

single precision Floating Point