Sunday, July 20, 2014

Implementation of FFT in decimation in time in verilog-

The Fast Fourier transform (FFT) is an algorithm that efficiently computes the discrete Fourier transform(DFT). In this particular implementation of FFT, which is capable of computing the fast Fourier transformation in case of decimation in time, when the number of inputs are eight.

In this particular design, implementation is done on the software Modelsim SE 6.5, using the hardware descriptive language verilog for designing. Furthermore using the concept of Folding as well as Retiming,
we can easily reduce the number of registers used in the normal FFT.

Difference can be easily seen as below :
(A.)FFT (without Folding & Retiming)



 Now, below is simulation window- FFT in DIT


(B.)FFT (with Folding & Retimin






  

Simulation window – FFT in Decimation in time


Author - Akash Kumar 
(Research Associate at Silicon Mentor)


Tags : Verilog Training in delhi - ncr , VLSI training in delhi NCR ,  M.tech final year Projects Guidance and supports