Thursday, November 6, 2014

What is ‘SETUP and HOLD’ time concept?


Gates is referred as the basic building blocks of combinational logic circuits. However there are XOR, NAND, NOR, XNOR gates too but particularly AND, OR, and NOT gates are used. Similarly, Flip flops are referred as the basic building blocks of sequential circuits. Flip flops are clock based devices. One bit is stored by each flip flop.

There are restrictive time regions around the clock for every flip flop. Input should not change in these time regions. These regions are called restrictive because by changing the input in this region the output is not sure, it may or may not be the one you expected. 

Output is derived from either the new input, the old input, or may be in between these two. The two most important terms in the digital clocking are defined below.
Setup and hold time.
  • The setup time is the time interval just before the clock where the data must be remain stable. Other definition is, “SETUP time is the minimum time before the clock's active edge that the data must be stable to be latched correctly in this period of time. It may cause incorrect data to be captured, if there is any violation, which is known as setup time violation.
  • Add caption
  • The hold time is the time interval after the clock where the data must be remain stable. It may cause incorrect data to be latched if there is any violation, which is known as a hold time violation.

  • Remedies for setup time violation:
    •    Optimize the combinational logic between the flip-flops to get minimum delay.
    •    To get lesser setup time, redesign the flip-flops.
    •    Play with clock skew (useful skews).


    Remedies for hold time violation
    :
          •    Use buffers to add delays
         .•    lockup-latches can be added (basically to avoid data slip).  


                                                                                                              Author - Poornima Sharma
                                                                                                              (Intern Design Engineer)