Friday, July 3, 2015

FPGA Design and Verilog HDL Projects List

1.      FPGA implementation of LDPC bit-flipping algorithm using Co-simulation.
2.      FPGA implementation of LDPC Decoder using min-sum algorithm.
3.      Implementation of AES for image encryption and decryption.
4.      Development and verification of SPI protocol.
5.      Development and verification of PPI protocol.
6.      Audio processing using digital filter using Co-simulation.
7.      Design of single precision (32-bit) Floating point ALU.
8.      Design and implementation of the 128-point FFT processor.
9.      Design and implementation of 16bit RISC Processor.
10.    FPGA implementation of the 12-bit Ternary multiplier.
11.    Design of ECG signal processing and denoising using co-simulation.
12.    Design of low power test pattern generator.
13.    A BIST TPG for Low Power Dissipation and High Fault Coverage
14.    Low-Transition LFSR for BIST-Based Applications
15.    Verilog Implementation of UART with BIST capability
16.    Verilog implementation of RSA cryptography algorithm.
17.    Verilog implementation of 64, 32, 16 and 8 bit CSA.
18.    Design of low power TPG using LP_LFSR for fault coverage.
19.    Design and implementation of the 32-point FFT processor by Folding Transform.
20.    FPGA implementation of the REDEYE detection and correction.
21.    FPGA implementation JPEG 2000 using 2-D DWT .
22.    Hardware implementation JPEG 2000 using DWT.
23.    Hardware implementation of the H.264 encoder for HD Video.
24.    Hardware implementation of the MPEG encoder.
25.    FPGA implementation of Quantization algorithms for multi standard video platform.
26.    FPGA implementation of the motion object detection based on background subtraction.
27.    FPGA implementation of the AES algorithm for reduced cycles.
28.    Design and implementation of the MRI image enhancement and denoising.
29.    Hardware implementation of the ECG (Arrhythmia).
30.    Fault tolerant deflecting router with high fault coverage for ON-Chip network.
31.    BIST implementation of the UART.
32.    Orientation field estimation for the fingerprint enhancement.
33.    Verilog implementation of Reconfigurable router (NOC).
34.    Verilog implementation of Decimal to binary conversion.
35.    Verilog implementation of 3D-DWT.

If you need any suggestion or research guidance for FPGA design & verilog HDL projects then feel free to contact us.

Friday, June 26, 2015

Low Power Digital VLSI Projects List

  • Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
  • 0-9 bit pattern recognition circuits using neural network, 3-bit pattern recognition.
  • An adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage Scalable Standard Cell Library.
  • Lewis grey comparator.
  • 4×4-Bit Array Two Phase Clocked Adiabatic Static CMOS Logic Multiplier with New XOR.
  • Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
  • Low Power D-latch design using MCML Tri-state Buffers.
  • Ultra Low Power NAND Based Multiplexer and Flip flop.
  • MOS Current Mode Logic Realization of Digital Arithmetic Circuits.
  • 0-0\9 digit pattern recognition circuit using neural network.
  • 6 transistors XOR and XNOR using FINFET.
  • Winner Take All Circuits of O (n) Complexity.
  • Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
  • Transmission gate based full adder in deep sub-micron technology.
  • Low power radix-4 booth multiplier using GDI logic.
  • High performance nibble multiplexer using modified adiabatic logic.
  • Sense energy recovery full adder working in sub-threshold region of operation.
  • Clock gated 4-bit Johnson counter using low power JK flip flop.
  • A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.
  • New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper.
  • Low Power, Delay Optimized Buffer Design using 70 nm CMOS Technology.
  • Clock gated 4-bit Johnson counter using low power JK flip flop.
  • Design of a novel low power 8-transistor 1-bit full adder cell.
If you need any suggestion or research guidance for Low Power Digital VLSI Projects then feel free to contact us.

Analog & Mixed Signal Design Projects List

  •    Common source amplifier.
  •    Flash ADC Architecture using Multiplexers to Reduce a Preamplifier and Comparator Count.
  •    Design of SRAM Cell from (6 transistors-12 transistors).
  •    6 Bit multiplexed based modified Flash Analog to Digital converter.
  •    Over Current protection circuit.
  •    TIQ based ADC.
  •    Low supply Voltage High performance CMOS current mirror.
  •    Low power quad node 10T soft error tolerant SRAM cell for space applications. (at 90nm).
  •    Power reduction technique for low power SRAM’s with high soft error tolerance.
  •    Design of long reset time Power on reset (POR) circuit with Brown out detection.
  •    Design and analysis low power two stage operational amplifiers at 180 nm.
  •    Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed and   low   Jitter PLL.
  •    Switched-current type of hamming neural network system for pattern recognition.
  •    Design of a Low-Voltage Low-Dropout Regulator.

If you need any suggestion or research guidance for Analog & Mixed Signal design projects then feel free to visit us.

Sunday, June 21, 2015

An overview of Research Guidance in PhD

Silicon Mentor is one of the best research entities in India. To make an environment of research we are providing our services in research and development of some of the world most recent burning topics in engineering and technology. Silicon Mentor has expertise in various research domain including Computer Vision, Machine Learning, VLSI, Biomedical Signal Processing and Digital Signal Processing. In the process of research and development we have a unit which provides research guidance to the PhD students. Our research process for PhD projects starts from the specific domain topic selection.

1)    The topic selection is based on either on the student requirement or we suggest them appropriate topic.
2)    After the selection of appropriate topic and research domain we assign our expert team for the support PhD student. This team works with the students on some of the previous work published in SCI indexed journals.
3)    During the review period of the previous work our team starts to generate new idea to modify the previous work.
4)    After the completion of previous work verification we turn our direction of research towards the modification in the previous design or to generate a new idea.
5)    For the implementation of new idea or modification we continuously contact the students and make him understand the new work.
6)    For the required tool training Silicon Mentor runs special class to train the students.
7)    After the modification of the design we do compare the result of the modified design and previous work.
8)    After the verification of complete verification of the result we forward this to next step.
9)    We do also compare analytical and simulative results for the preparation of the proposed method.
10)    After the completion of the all above steps we provide our expert team in the domain of research paper publication.
11)    Our expert team of Research paper publication provides updates about the new conference and journal publication.
12)    We usually suggest our clients to publish their work in IEEE, Springer like publications.
13)    We also help them to publish their work in any of the SCI index journals.

Thus we try to provide best research guidance for PhD thesis and PhD projects. We are in the process of continuous improvement to make our services more convenient in the area of Research and Development. For more information you can contact us.

Tuesday, June 9, 2015

How to make an FPGA Partially Reconfigurable

Partially reconfiguration means changing the FPGA partially or only the selected part of the FPGA is reconfigured. It can be done in two ways:

i)    Module based partial reconfiguration
Partial reconfiguration on the basis of difference

Module based partial reconfiguration:

In module based reconfiguration we reconfigure on the specific module or only by changing a selected module we can do the partially reconfiguration of our FPGA. The portions of the design to be reconfigured are known as reconfigurable modules. Specific properties and specific layout criteria must be met with respect to a reconfigurable module, FPGA design intending to use partial reconfiguration must be planned and laid out with that in mind.

Partial reconfiguration on the basis of difference:

Partial reconfiguration on the basis of difference is a method of making small changes in an FPGA design, such as changing I/O standards, LUT equations, and block RAM content.


i)    To lessen power or making the design power-efficient.
ii)    Through the JTRS Program, SDRs are becoming a reality for the defense industries as an effective and necessary tool for communication. SDRs assure the JTRS standard by having both a software-reprogrammable operating environment and the ability to support multiple channels and networks simultaneously.
iii)    Partial reconfiguration is useful in a variety of applications across many industries. The aerospace and defense industries have certainly taken advantage of its capabilities.
iv)    Increased system performance. Although a portion of the design is being reconfigured, the rest of the system can keep on to operate. There is no loss of performance or functionality with unaffected portions of a design.
v)    Hardware sharing. Because partial reconfiguration allows you to run multiple applications on a single FPGA, hardware sharing is realized. Benefits include reduced device count, reduced power consumption, smaller boards, and in particular lower costs.

key steps used in Xilinx to make the FPGA partially Reconfigured:

1: First Create Processor Hardware System.
2: Then Create Software Project.
3: After then Create a Plan ahead Project.
4: Defining a Reconfigurable Partition.
5: Adding Reconfigurable Modules.
6: significant the Reconfigurable Partition Region.
7: Running the Design Rule Checker.
 8: Then Create the First Configuration, Implementing, and Promoting.
9: Then Create Other Configurations, and Implementing.
10: Then Run Partial Reconfiguration to Verify Utility.
11: Generating Bit Files.
12: Creating an Image, and Testing.


There are many advantages to make the FPGA reconfigured. only some from them are following:

I)    To make the device more efficient.
II)    To lessen the LUTs of the design by replacing only specific portion.
III)    To lessen power of the design by replacing only specific portion.
IV)    To lessen the delay of the design by replacing only specific portion or a specific module.


Monday, June 1, 2015

Is It The Right Path To Pursue PhD Research?

PhD research is the highest level of academic research conducted in universities and institutes throughout the World. The methods used to conduct Ph.D. research are sound and the data that results from the research must be unique. There are many techniques has been created such as scientific methodologies have been created to ensure the soundness and uniqueness of doctoral research and to secure continuity in research results. The most often employed methodologies are quantitative methods, qualitative methods, comparative methods and clinical trials.

The world is producing a large number of PhD holders and their number is increasing every year. Therefore in this era how can a normal PhD holder can survive? World’s most population countries India and China producing more than 40,000 PhD every year. Most of the PhD has completed their research in a short duration which results in the quality of the graduates is not consistent. And Most of the PhD remains unemployed.

In our research whenever we think of doing the research we always think of  doing something innovative  which can change the world but when we come for real implementation of the idea we found only few things have done in our PhD research. The few things which done usually during PhD seems to be unique. What should we do? And, how to do? It depends on one’s circumstances but the research should contribute something new in the specific domain. 

Silicon Mentor is a place where many new researchers are working together to make something innovative and unique. These young researchers help the research students to pursue their research with some of the unique methodologies. Silicon Mentor have Expertise in different Domain such as Computer vision , Biomedical Research, Digital Signal Processing, Machine Learning , Low Power VLSI , Mixed Signal VLSI , FPGA implementation.

Thursday, May 21, 2015

Road and Lane Detection: Different Scenarios and Models

Advanced Driver Assistance Systems are an integral part of vehicles today. They can be passive, as in merely alerting the driver in case of emergencies, or actively respond by taking over vehicle controls during emergency scenarios. Such systems are expected to reach full autonomy during the next decade. The two major fields of interests in the problem are: road and lane perception, and obstacle perception. The former involves finding out road and lane markers, to ensure that vehicle position is correct, and to prevent any departures. Obstacle detection is necessary to prevent collisions with other traffic, or real-life artifacts like streetlights, stray animals, pedestrians, etc.

Problem Scope

Road and lane perception include detecting the extent of the road, the number and position of lanes, merging and splitting lanes, over different scenarios like urban, highway or cross-country. While the problem seems trivial given recent advancements in image processing and feature detection algorithms, the problem is complicated by the presence of several challenges, such as:

•    Case diversity: Due a verity of real-world parameters, the system has to be tolerant of a huge diversity of incoming parameters. These include:
  1.     Lane and Road appearance: Color, texture and width of lanes. Road color, width and curvature differences.
  2.     Image clarity: Presence of other vehicle, shadows cast by objects, sudden changes in illumination.
  3.     Visibility conditions: Wet roads, presence of fog or rain, night-time conditions.
•    High reliability demands: In order to be useful and acceptable, the assistance system should achieve very low error rates. A high rate of false positives will lead to driver irritation and rejection, while false negatives will cause system compromise and low reliability.

Modalities Used

The state-of-the-art research and commercial systems are looking at several perception modalities s sensors. A quick view at their operation and pros-cons is presented here:

1.    Vision: Perhaps the most intuitive approach is to use vision based systems, as lane and road markers are already optimized for human vision detection. Use of front-mounted cameras is nearly standard approach in almost all systems, and it can be argued that since most of the signature of lane marks is in the visual domain, no detection system can totally ignore the vision modality. However, it must be stressed that the robustness of the current state-of-the-art processing algorithms is far from satisfactory, and they also lack the adaptive power of a human driver.

2.    LIDAR: The most emerging technology is the use of Light Detection and Ranging sensors, which can produce a 3D structure of the vehicle surrounding, thereby increasing robustness as obstacles are more easily detected in 3D. In addition, LIDARs are active sources- thus they are more illuminance adaptive. The LIDAR sensors are however very expensive.

3.    Stereo-vision: Stereo-vision uses two cameras to obtain the 3D information, which is much cheaper in terms of hardware, but requires significant software overhead. It also has poorer accuracy, and leads to more probability error.

4.    Geographic Information Systems: The use of prior geographic database together with known host-vehicle position can in effect replace the on-board processing requirement and enable worldwide ‘blind’ autonomous driving. However, the system needs very accurate positioning in terms of resolution of the vehicle position, as well as updating the geographic database in real-time with changing traffic dynamics and obstacle positions, either by satellite imagery or GPS measurements. The uncertainty in obtaining and updating highly accurate map information over large terrains has constrained it as a complementary tool to on-board processing.

5.    Vehicle Dynamics: The presence of sensors like Inertial Measurement Units (IMUs) provides insight into the motion parameters of the vehicle such as speed, yaw rate and acceleration. This information is used in the temporal integration module, to relate data across several time-frames.

Generic Solutions

The road and lane detection problem can be broken into the following functional modules. The implementation of said modules uses different approaches across different research and commercially available systems, but the ‘generic system’ presented here is present as the holistic skeleton for them.

1.    Image Cleaning: A pre-filer is applied to the image to remove most of the noise and clutter, arising from obstacles, shadows, over and under exposure, lens flare and vehicle artifacts. If training data is available or data from previous frames is harnessed, a suitable region of interest can be extracted from the image to reduce processing.

2.    Feature Extraction: Based on the required subtask low-level features such as road texture, lane marker color and gradient, etc. are extracted.

3.    Model Fitting: Based on the evidence gathered, a road-lane model is fitted to the data.

4.    Temporal Integration: The model so obtained is reconciled with the model of the previous frames, or the GPS data if available for the region. The new hypothesis is accepted if the difference is explainable based on the vehicle dynamics.

5.    Post Processing: After computation of the model, this step involves translation from image to ground coordinates, and data gathering for use in processing of subsequent frames.

Future Prospects

In concluding remarks, we can stress that road and lane segmentation are fundamental problems of Driver Assistance Systems. The extent of complexity can range from passive Lane Departure Warning systems to fully autonomous ‘blind’ drivers. The next step forward is to extend the scope of current detection techniques into new domains, and to improve its reliability. The first requires a better understanding and development of new road-scene models that can capture multiple lanes, non-linear topographies and other non-idealities successfully. The reliability challenge is harder, especially for closed-loop systems, where even small error rates may propagate. It might become essential to include modalities other than vision, and incorporate machine learning to train algorithms better.


Tuesday, May 19, 2015

Surround View System for Vehicles and its Advantages for Drivers

ADAS - Advanced Driving Assistance System is a very popular research area all around the globe and has unbelievable future scope. Within ADAS, the latest developing area and market is of Surround view system or Surround vision or Top view system. These systems are meant to provide a central display of the vehicle to the driver from the perspective of a bird's vision.  Hence, another name given to such systems is "Birds' eye view". A glimpse of Surround vision is shown in the figure below. As the name suggests, surround view system provides the view of immediate surroundings to the drivers. Such views are of great assistance to the drivers in precise operations viz., parking maneuvers, driving in heavy traffic conditions etc.

Any bird eye vision system typically involves 4-6 wide angle fish-eye lens cameras mounted all around the vehicle. The installed/mounted cameras have Field of View up to 180 degrees. Such lenses are preferred so that immediate surrounding is completely visible even after the data loss during the implementation of algorithm on captured frames. 

Two types of camera arrangements are generally seen: 

  • 4 cameras: front, back and one on each side view mirrors.
  • 6 cameras: 1 on all four corners, front and back.
Out of these two, the former is most common because of reasons like lesser complications, initial cost-effectiveness etc.

Advantages to Drivers:
  1. Assistance in parking maneuvers because surrounding vehicles and parking slots are easily visible and driver can solely focus on driving rather than peeping into the mirrors for parking safely.
  2. Eliminates the use of mirrors by providing the complete view of surrounding on a single screen.
  3. Any object or vehicle approaching or running close to the vehicle is visible at once.
  4. Being "top-view", the system is free of perspective distortion. In layman's language, drivers are free of constraints like "Objects in the mirror are closer than they appear".
  5. Works properly even on slopes because of reasonably large field of view.
  6. Driver error is reduced or even eliminated, and efficiency in traffic and transport is enhanced.
  7. High-performance driving can be conducted regardless of the vision, weather and environmental conditions.
  8. Many more vehicles can be accommodated, on regular highways but especially on dedicated lanes