Thursday, January 8, 2015

WHAT ARE DIFFERENT CMOS POWER REDUCTION TECHNIQUES?

As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (Vth) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (Vth) devices are used as they switch faster, but the problem with low Vth devices is that they have substantially high leakage power. In order to minimize static leakage power high Vth devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low Vth devices are used. High Vth devices are turned on inactive mode and off in sleep mode.
Fig1: MTCMOS Circuit


Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.


DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously.