An Edge to VLSI Implementation of Digital Signal Processing Algorithms

The implementation of digital signal processing algorithms and availability of the digital systems have become more widespread since last two decades due to easy availability of digital systems. Earlier analog processors were used to perform the signal processing due to unavailability of digital processors.

The digital signal processing became feasible to be performed in real time in the recent times due to hardware implementation of the algorithms developed in signal processing. It is all because of the requirement of higher level computations in the signal processing especially for the real time applications.

The demands for the high level computation systems combined with the performance of the VLSI architectures which led to the development of VLSI Digital signal processors such as TMS320(1982) and DSP56001(1987). The developers are left with enormous specific architectures of DSP with the ease in development of VLSI designs.

The most common and usually employable DSP techniques are the FFT computing, FIR and IIR digital filters. These techniques require the three basic operations i.e. multiplication, storage and addition and these operations can easily be performed with the VLSI oriented architectures for Digital signal processing architectures. 

The architectures developed through the VLSI implementation for DSP applications generally make use of parallel processing, multiprocessing, array processors, RISC i.e. Reduced instruction set and  pipelining for the very high processing.

The architectures developed for the Digital signal processing applications are tested and brought to the real time implementation through VLSI only. The most commonly and preferably used hardware for the implementation of DSP algorithms in VLSI is the FPGA. FPGA implementation of the digital signal processing algorithms makes it possible to develop a VLSI architecture for the high computation processing and multiprocessing at the real time.