Wednesday, January 28, 2015


Body biasing is the change in transistor threshold voltage because of voltage difference between the transistor source and body. As the voltage difference between source and body effect the threshold voltage of any transistor, so body can be considered as a second gate to determine when transistor will turn on or off. Body coefficient “gamma” determines the strength of body effect. Body effect is diminished with transistor scaling, instead transistor body is connected to power (VDD) for p-channel transistor and to ground for n-channel transistor.

Body Bias:

It involves connecting the body of transistor either to ground or power supply. The body biasing can be applied to transistor either by using off-chip (external) source or by using on-chip (internal) source. In on- chip approach, reverse body bias voltage is provided by charge pump circuit and forward bias voltage is provided by voltage divider circuit. In reverse body biasing we apply negative body-to-source voltage to an n-channel transistor which raises transistor threshold voltage but on the other hand make transistor both slower and less leaky. In forward body biasing we apply positive body-to-source voltage to a p-channel transistor which lowers transistor threshold voltage but on the other hand make transistor both faster and leakier.

Body Bias Methodologies:

·         Fixed Body Bias

In this methodology a fixed body bias voltage is applied to all chips in which body bias value is set during design. In power gating transistor a fixed forward bias voltage is applied during the on state to reduce the on-resistance of the transistor switch and a fixed reverse bias voltage is applied during the off state to reduce the remaining leakage in the power-gated block.

·         Adaptive Body Bias

In this methodology different fixed body bias voltage is calibrated at production test. When forward body bias voltage is applied to slow chip it lowers the threshold voltage and speeds up the chip and when reverse bias voltage is applied to a fast chip it increases transistor threshold voltage and reduces the excess leakage current (and leakage power consumption) of the chip.

·         Dynamic Body Bias

In this methodology the body bias voltage is changed multiple times while the chip is operating rather than setting the body bias just once either during design or at production test. This methodology is also used to reduce temperature and aging effects and it will manage power management modes more effective so that it can optimize very low power operation.

Dynamic body bias can adjust the transistor threshold voltage to compensate for changes in the transistor as the product ages and also adjust threshold voltage of transistor to compensate for temperature related changes in the threshold voltage for transistor as the part heats up and cools down, maintaining more uniform power and leakage.

Thursday, January 8, 2015


As the technology continues to scale down to the deep submicron process, leakage power consumption has become a major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry.

MTCMOS (Multiple Threshold CMOS)- It is a variation of CMOS chip technology in which transistors are there with multiple threshold voltages (Vth) for the purpose of reducing delay and power in circuits. In order to minimize clock periods on critical delay paths, low threshold (Vth) devices are used as they switch faster, but the problem with low Vth devices is that they have substantially high leakage power. In order to minimize static leakage power high Vth devices are used on non-critical paths. Sleep Transistors technique is used in MTCMOS for reducing power. When fast switching speed is required than low Vth devices are used. High Vth devices are turned on inactive mode and off in sleep mode.
Fig1: MTCMOS Circuit

Power Gating- In this technique power consumption is reduced, by not passing currents to those blocks that are not in use. In low threshold transistors sub-threshold leakage current is more, so in order to suppress the high subthreshold leakage current, high sub-threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines. These high threshold voltages power supply and ground switches are controlled by a sleep signal. During active mode, these switches are on, providing virtual power and ground lines for the logic circuits and during standby mode, these switches are off to reduce sub-threshold leakage current.

DTCMOS (Dual Threshold CMOS)- In this technology high threshold transistor are applied on non-critical path to reduce the sub-threshold leakage and performance is maintained by low threshold transistors in critical paths. So no additional transistors are required and performance as well as low power can be achieved simultaneously.